This invention relates to high power, high speed bipolar transistors, and more specifically relates to a novel planar emitter pattern and a novel process of manufacture therefor.
High speed bipolar transistors are well known and have application in any desired high switching speed application, such as for power inverters or the like. It is known that switching speed can be improved if the planar emitter area of a transistor has a shallow depth in its central portions and a greater depth in its outer periphery. In addition, the central shallow region of the emitter should have a higher doping concentration than the deeper, outer peripheral region. This geometry minimizes the number of minority carriers injected beneath the emitter during turn on, which minority carriers are difficult to sweep out rapidly during turn off. Thus, switching speed will be increased.
The manufacturing process previously used to shape the emitter junction as discussed above, and to control its conductivity to have lower conductivity at its center than its outer rim, was complex and expensive. In addition, high speed switching transistors using the shaped planar emitter region described above have not had the highest possible voltage breakdown values because the field beneath the emitter does not spread out over the full area of the device under high blocking voltage.
Prior art shaped emitter structures of the type discussed above are shown in a paper entitled A NEW POWER TRANSISTOR STRUCTURE FOR IMPROVED SWITCHING PERFORMANCES by K. Owyang and P. Shafer, which was delivered at the International Electron Devices Meeting of the I.E.E.E. in 1978.